1. Field
This disclosure relates generally to techniques that allow a user level instruction to initiate the movement of a block of data via a system bus write command and, more specifically, to techniques for performing a system bus write command while ensuring permission protections by an underlying operating system.
2. Related Art
In various applications, user programs (user code) may need to build data structures or packets in system memory to facilitate transmission of the data structures or packets out of the system memory to an input/output (I/O) device (e.g., a networked device) or a coprocessor. To transfer data from user code to an I/O device a conventional approach has: built a packet that includes data at location ‘A’ in a system memory; loaded the data from the location ‘A’ in the system memory into general purpose registers (GPRs) of a processor core; and stored the data in the GPRs to location ‘B’ in the system memory. In general, because a user program works in ‘effective address’ space, a processor core has been responsible for converting both address ‘A’ and address ‘B’ from effective addresses (used by software) to real addresses (used by hardware) and checking permissions to ensure that the user code (which may correspond to a thread) is allowed to access a page or pages of the system memory at the addresses ‘A’ and ‘B’. By performing an effective-to-real address translation and a permission check, a hypervisor has controlled what real address space user code has been allowed to access. In the case where user code is attempting to send a relatively large amount of packets (to, for example, be transmitted over a network), the conventional approach can greatly limit the number of packets that can be built and transmitted in a given amount of time. Moreover, the conventional approach utilizes valuable bandwidth (in moving data through GPR registers of a processor core) that may be utilized by the processor core to perform other tasks.